1. Field of the Invention
The present invention relates to a interconnect for semiconductor device, and more particularly to an improved plug forming method for a semiconductor device wherein a plug of polysilicon material is formed in a contact hole.
2. Description of the Background Art
As accompanied by a large integration of a semiconductor device, a bit line contact hole and a node contact hole for a capacitor are significantly being decreased in size, thereby increasing an aspect ratio of a contact hole. Accordingly, when an interconnection is formed in a subsequent step, a polysilicon plug or a cylinder is formed inside a contact hole to prevent a short of the interconnection, and then a conductive interconnection is formed on the polysilicon plug or the cylinder according to a generalized interconnection forming method.
A plug forming method for a semiconductor device according to the background art will now be described.
As shown in FIG. 1, the semiconductor device for forming a plug according to the background art includes a semiconductor substrate 1 having a plurality of diffusion region 2 in the surface of the semiconductor substrate 1. An insulation layer 3 is formed on the semiconductor substrate 1, and the insulation layer 3 is partially etched over a diffusion region 2 formed in the semiconductor substrate 1 to form contact holes 4a, 4b or openings. Here, contact hole 4a is narrower in width than the contact hole 4b.
FIG. 2 is a cross-sectional view of a semiconductor device in which a polysilicon layer 5 is deposited on the structure of FIG. 1.
Referring to FIG. 3A, the polysilicon layer 5 of FIG. 2 is etched back to obtain plugs 5a, 5b or cylinders in the contact holes 4a, 4b. The etchback step employs an anisotropic etching method in which there is used a fluorine based plasma including a fluorine-containing gas such as SF.sub.6, CF.sub.4, and CHF.sub.3, or a compound gas mixed by the fluorine-containing gas and a Cl.sub.2. As shown in FIG. 3A, although the surface of the insulation layer 3 is smooth, there remain residues 6 formed of polymer. Also, the respective upper surfaces of the polysilicon plugs 5a, 5b is much lower in level than the upper surface of the insulation layer 3. Here, it is referred to as a plug loss that the upper surface of the plug is partially etched and removed to become lower than the upper surface of the insulation layer 3. Also, it should be understood that such a plug loss occurs more seriously in the polysilicon plug 5a formed in the relatively narrow contact hole 4a than in the polysilicon plug 5b formed in the relatively wide contact hole 4b. The loss difference between the plugs 5a, 5b occurs due to a loading effect during the etching step. In other words, the loading effect denotes that the smaller the etching target area, the more increased becomes the concentration of the etchant species, thereby increasing the etching steed.
As shown in FIG. 3B illustrating a cross-sectional view of a semiconductor device wherein a compound gas plasma mixed by a chlorine-containing gas such as Cl.sub.2 and HCl, and a hydrogen bromide (HBr) and wherein the polysilicon plugs 5a, 5b or cylinders are formed. Therein, the surface of the insulation layer 3 is significantly rough and there is shown a plug loss.
After the etchback step as shown in FIGS. 3A, 3B, there is carried out a wet etching step to remove the residues 6 remaining along the entire structure on the semiconductor substrate 1.
As shown in FIG. 3A, when the polysilicon plug is formed using a conventional fluorine gas plasma, there is an advantage in that a smooth surface of the insulation layer is obtained. However, it is a disadvantage in that there occurs a serious plug loss as well as a critical loading effect.
Meanwhile, as shown in FIG. 3B, when there is employed a chlorine gas plasma, although the plug loss is not so critical, the loading effect becomes large. Further, the surface of the insulation layer disadvantageously becomes rough after the etchback step. When the surface of the insulation layer becomes rough, since the residues remain in the eaten-up surface of the insulation layer, the subsequent steps may cause a short effect to the interconnection, thereby deteriorating the reliability of the semiconductor device.
Further, when the HBr gas is added to the chlorine gas, although the roughness of the surface is more or less improved, the steps may be difficult for their reproducing.